The integrated circuit (IC) design is more challenging when semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. The performance of a chip design is seriously influenced by the control of resistance/capacitance (RC), timing, leakage, and topology of the metal/dielectric inter-layers.
To satisfy the criterion of mask-making, the enforcement of mask rule check (MRC) after optical proximity correction (OPC) is indispensable. The design pattern is adjusted to meet the specification of mask-making and the mask manufacturing capability. However, the enforcement of MRC leads to the erosion and reduction of the simulated contour hitting the target. All circuit layers in sub-45 nm generations face the dilemma between the simulated contour hitting the target and the MRC enforcement.
Therefore, what is needed is a method and a system to provide effective IC design for the advanced IC technologies addressing the above problems and reducing the patterning impact from the MRC enforcement.